1. Field of the Invention
The invention relates to a semiconductor device suitable for use as an electrostatic breakdown protection device.
2. Description of the Related Art
In a semiconductor integrated circuit, in order to prevent a breakdown (an electrostatic breakdown) due to a surge voltage such as static electricity, an overvoltage, electromagnetic noises emitted from peripheral devices or the like, a protection device (hereafter, referred to as an electrostatic breakdown protection device) is provided near input and output terminals.
There is an electrostatic breakdown protection device using a bipolar transistor as well as ones using a diode or a MOS transistor. A device structure of a conventional NPN-type bipolar transistor provided as an electrostatic breakdown protection device will be described referring to FIGS. 5A and 5B. FIG. 5A is a plan view showing the bipolar transistor and FIG. 5B is a cross-sectional view of FIG. 5A along line Y-Y.
An N− type epitaxial layer 101 is formed on a front surface of a P type semiconductor substrate 100, and an N+ type embedded layer 102 is formed on the bottom of the epitaxial layer 101. Furthermore, a P+ isolation layer 103 for dividing the epitaxial layer 101 into a plurality of island regions is formed. The P+ isolation layer 103 has a structure in which an upper isolation layer 103a and a lower isolation layer 103b where P type impurities are added are joined inside the epitaxial layer 101.
A P impurity layer 104 is formed as a base region on the front surface of the epitaxial layer 101, and an N+ impurity layer 105 is formed as an emitter region on the front surface of the P impurity layer 104. Furthermore, an N+ impurity layer 106 is formed on the front surface of the epitaxial layer 101, and the epitaxial layer 101 and the N+ impurity layer 106 form a collector region. Furthermore, an insulation film 107 is formed on the epitaxial layer 101, and a base electrode 108 connected to the P impurity layer 104, an emitter electrode 109 connected to the N+ impurity layer 105, and a collector electrode 110 connected to the N+ impurity layer 106 are formed on this insulation film 107. The base electrode 108 and the emitter electrode 109 are electrically connected through a wiring (not shown). This connection is generally called diode connection.
As described above, the conventional NPN-type bipolar transistor used as an electrostatic breakdown protection device has a structure in which the emitter region (the N+ impurity layer 105) is provided between the N+ impurity layer 106 and the base electrode 108 and the electrodes for the collector, the emitter and the base are provided from the left to the right in this order as shown in FIGS. 5A and 5B.
A relation of a voltage V applied between the collector and the emitter and an emitter current I in this bipolar transistor has characteristics as shown in FIG. 6. Vs is referred to as a snapback voltage and Vh is referred to as a hold voltage.
In order to function as an electrostatic breakdown protection device, the transistor need be designed so that its snapback voltage Vs is lower than a breakdown voltage of a device to be protected. On the other hand, in order to prevent malfunction of the electrostatic breakdown protection device due to latch-up, the transistor need be designed so that its hold voltage Vh is at the operation power supply voltage of the semiconductor integrated circuit or higher. Thus the characteristics of the snapback voltage Vs and the hold voltage Vh are important for designing the electrostatic breakdown protection device.
Supposing the length between the P impurity layer 104 and the N+ impurity layer 106 is t and the length between the end of the P impurity layer 104 on the N+ impurity layer 106 side and the N+ impurity layer 105 is d as shown in FIGS. 5A and 5B, it is known that the device has the following relation (Japanese Patent Application Publication No. hei 10-214905): the hold voltage Vh increases by increasing the value of d and (2) the snapback voltage Vs increases by increasing the value of t.
Therefore, the snapback voltage Vs and the hold voltage Vh are adjusted by adjusting the values of t and d so as to provide desired operation characteristics to the bipolar transistor as the electrostatic breakdown protection device.
The above described technique and the relevant technique to this are described in Japanese Patent Application Publication No. hei 10-214905 and “Design And Analysis of New Protection Structures for Smart Power Technology with Controlled Trigger and Holding Voltage” (2001), IEEE-IRPS ESD/LATCHUP (session 3D-6), P253.
As described above, a hold voltage Vh need be set at an operation power supply voltage of a semiconductor integrated circuit or more. Therefore, it has been conceived that a high hold voltage Vh is obtained by increasing the value of d when a bipolar transistor having the described structure is used as an electrostatic breakdown protection device.
However, it is found from a result of an experiment conducted by the inventor that even if the value of d is increased in the conventional structure, the increase of the hold voltage Vh relative to the increase of d tends to gradually saturate as shown by VH1 in FIG. 2. Therefore, in the conventional structure, the countermeasure of increasing the value of d sometimes has a difficulty in increasing a hold voltage Vh enough. Furthermore, there is a problem that the increase of the value of d leads to the increase of the size of the electrostatic breakdown protection device.
Accordingly, the invention is directed to providing a technique of increasing a hold voltage more than conventional when a bipolar transistor is used as an electrostatic breakdown protection device and preventing the size of the protection device from increasing.